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10.7 Gbps Active Back-Termination, Differential Laser Diode Driver ADN2525
FEATURES
Up to 10.7 Gbps operation Very low power: 670 mW (IBIAS = 40 mA, IMOD = 40 mA) Typical 24 ps rise/fall times Full back-termination of output transmission lines Drives TOSAs with resistances ranging from 5 to 50 PECL-/CML-compatible data inputs Bias current range: 10 mA to 100 mA Differential modulation current range: 10 mA to 80 mA Automatic laser shutdown (ALS) 3.3 V operation Compact 3 mm x 3 mm LFCSP package Voltage input control for bias and modulation currents XFP-compliant bias current monitor Optical evaluation board available
GENERAL DESCRIPTION
The ADN2525 laser diode driver is designed for direct modulation of packaged laser diodes having a differential resistance ranging from 5 to 50 . The active back-termination technique provides excellent matching with the output transmission lines while reducing the power dissipation in the output stage. The back-termination in the ADN2525 absorbs signal reflections from the TOSA end of the output transmission lines, enabling excellent optical eye quality to be achieved even when the TOSA end of the output transmission lines is significantly misterminated. The small package provides the optimum solution for compact modules where laser diodes are packaged in low pin-count optical subassemblies. The modulation and bias currents are programmable via the MSET and BSET control pins. By driving these pins with control voltages, the user has the flexibility to implement various average power and extinction ratio control schemes, including closed-loop control and look-up tables. The automatic laser shutdown feature allows the user to turn on/off the bias and modulation currents by driving the ALS pin with the proper logic levels. The product is available in a space-saving 3 mm x 3 mm LFCSP package specified from -40C to +85C.
APPLICATIONS
SONET OC-192 optical transceivers SDH STM-64 optical transceivers 10 Gb Ethernet optical transceivers XFP/X2/XENPAK/XPAK/MSA 300 optical modules SR and VSR optical links
FUNCTIONAL BLOCK DIAGRAM
VCC VCC VCC ALS
ADN2525
IMODP IMOD 50 VCC IMODN
50
50 GND
DATAP DATAN IBMON IBIAS 800 800
200
200
200
2
02461-001
MSET
GND
BSET
Figure 1. Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2005 Analog Devices, Inc. All rights reserved.
ADN2525 TABLE OF CONTENTS
Specifications..................................................................................... 3 Thermal Specifications ................................................................ 4 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ........................................................................ 9 Input Stage..................................................................................... 9 Bias Current .................................................................................. 9 Automatic Laser Shutdown (ALS) ........................................... 10 Modulation Current................................................................... 10 Load Mis-termination ............................................................... 12 Power Consumption .................................................................. 12 Applications Information .............................................................. 13 Typical Application Circuit....................................................... 13 Layout Guidelines....................................................................... 13 Design Example.......................................................................... 14 Headroom Calculations ........................................................ 14 BSET and MSET Pin Voltage Calculation .......................... 14 Outline Dimensions ....................................................................... 15 Ordering Guide .......................................................................... 15
REVISION HISTORY
3/05--Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADN2525 SPECIFICATIONS
VCC = VCCMIN to VCCMAX, TA = -40C to +85C, 50 differential load resistance, unless otherwise noted. Typical values are specified at 25C, IMOD = 40 mA. Table 1.
Parameter BIAS CURRENT (IBIAS) Bias Current Range Bias Current while ALS Asserted Compliance Voltage1 MODULATION CURRENT (IMODP, IMODN) Modulation Current Range Modulation Current while ALS Asserted Rise Time (20% to 80%)2, 3 Fall Time (20% to 80%)2, Random Jitter2, Deterministic Jitter3, 4 Differential |S22|
3 3
Min 10 0.6 0.6 10
Typ
Max 100 100 VCC - 1.2 VCC - 0.8 80 0.5 32.5 32.5 0.9 12
Unit mA A V V mA diff mA diff ps ps ps rms ps p-p dB dB V Gbps V p-p diff dB mA/V mA/V A/mA % % % % V V A A s s
Test Conditions/Comments
ALS = high IBIAS = 100 mA IBIAS = 10 mA RLOAD = 5 to 50 differential ALS = high
24 24 0.4 7.2 -10 -14 VCC - 1.1
5 GHz < F < 10 GHz, Z0 = 50 differential F < 5 GHz, Z0 = 50 differential
Compliance Voltage1 DATA INPUTS (DATAP, DATAN) Input Data Rate Differential Input Swing Differential |S11| Input Termination Resistance BIAS CONTROL INPUT (BSET) BSET Voltage to IBIAS Gain BSET Input Resistance MODULATION CONTROL INPUT (MSET) MSET Voltage to IMOD Gain MSET Input Resistance BIAS MONITOR (IBMON) IBMON to IBIAS Ratio Accuracy of IBIAS to IBMON Ratio
VCC + 1.1 10.7 1.6 -16.8 100 100 1000 88 1000 10 115 120 1200 110 1200
0.4 85 75 800 70 800
NRZ Differential ac-coupled F < 10 GHz, Z0 = 100 differential Differential
See Figure 29
-5.0 -4.0 -2.5 -2
+5.0 +4.0 +2.5 +2
10 mA IBIAS < 20 mA, RIBMON = 1 k 20 mA IBIAS < 40 mA, RIBMON = 1 k 40 mA IBIAS < 70 mA, RIBMON = 1 k 70 mA IBIAS < 100 mA, RIBMON = 1 k
AUTOMATIC LASER SHUTDOWN (ALS) VIH VIL IIL IIH ALS Assert Time ALS Negate Time POWER SUPPLY VCC ICC5 ISUPPLY6
1 2
2.4 -20 0 0.8 +20 200 10 10
Rising edge of ALS to fall of IBIAS and IMOD below 10% of nominal; see Figure 2 Falling edge of ALS to rise of IBIAS and IMOD above 90% of nominal; see Figure 2
3.07
3.3 39 157
3.53 45 176
V mA mA
VBSET = VMSET = 0 V VBSET = VMSET = 0 V. ISUPPLY = ICC + IMODP + IMODN
Refers to the voltage between the pin for which the compliance voltage is specified and GND. The pattern used is composed by a repetitive sequence of eight 1s followed by eight 0s at 10.7 Gbps. 3 Measured using the high speed characterization circuit shown in Figure 3. 4 The pattern used is K28.5 (00111110101100000101) at 10.7 Gbps rate. 5 Only includes current in the ADN2525 VCC pins. 6 Includes current in ADN2525 VCC pins and dc current in IMODP and IMODN pull-up inductors. See the Power Consumption section for total supply current calculation.
Rev. 0 | Page 3 of 16
ADN2525
THERMAL SPECIFICATIONS
Table 2.
Parameter J-PAD J-TOP IC Junction Temperature Min 2.6 65 Typ 5.8 72.2 Max 10.7 79.4 125 Unit C/W C/W C Conditions/Comments Thermal resistance from junction to bottom of exposed pad. Thermal resistance from junction to top of package.
ALS
ALS NEGATE TIME
t IBIAS AND IMOD 90%
10%
t
02461-002
ALS ASSERT TIME
Figure 2. ALS Timing Diagram
VEE
VEE
VEE GND 10 10nF GND
VBSET TP1
1k TP2
BSET IBMON IBIAS GND Z0 = 50 10nF Z0 = 50 J2 GND GND GND Z0 = 50 10nF Z0 = 50 J3 GND GND GND VCC GND MSET NC1 ALS DATAN VCC
GND VCC GND Z0 = 25 GND Z0 = 25
GND BIAS TEE 35 Z0 = 50 ADAPTER ATTENUATOR OSCILLOSCOPE ADAPTER ATTENUATOR 50 BIAS TEE GND GND GND 50 GND
ADN2525
DATAP IMODP
IMODN GND VCC GND
GND 70 Z = 50 35 0 GND
VMSET VEE J8 GND J5 GND VEE
10nF
GND VEE
BIAS TEE: Picosecond Pulse Labs Model 5542-219 Adapter: Pasternack PE-9436 2.92mm female-to-female adapter Attenuator: Pasternack PE-7046 2.92mm 20dB attenuator
02461-003
22F GND
Figure 3. High Speed Characterization Circuit
Rev. 0 | Page 4 of 16
ADN2525 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Supply Voltage, VCC to GND IMODP, IMODN to GND DATAP, DATAN to GND All Other Pins Junction Temperature Storage Temperature Soldering Temperature (Less than 10 sec) Min -0.3 VCC - 1 .5 VCC - 1.8 -0.3 -65 Max +4.2 4.75 VCC - 0.4 VCC + 0.3 150 +150 240 Unit V V V V C C C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 5 of 16
ADN2525 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
15 DATAN 14 DATAP 16 VCC 13 VCC
MSET 1 NC 2 ALS 3 GND 4
PIN 1 INDICATOR
12 BSET 11 IBMON 10 IBIAS 9 GND
ADN2525
TOP VIEW
VCC 5
IMODN 6 IMODP 7
VCC 8
Figure 4. Pin Configuration
Note: The exposed pad on the bottom of the package must be connected to the VCC or GND plane.
Table 3. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Exposed Pad Mnemonic MSET NC ALS GND VCC IMODN IMODP VCC GND IBIAS IBMON BSET VCC DATAP DATAN VCC Pad I/O Input N/A Input Power Power Output Output Power Power Output Output Input Power Input Input Power Power Description Modulation Current Control Input No Connect--Leave Floating Automatic Laser Shutdown Negative Power Supply Positive Power Supply Modulation Current Negative Output Modulation Current Positive Output Positive Power Supply Negative Power Supply Bias Current Output Bias Current Monitoring Output Bias Current Control Input Positive Power Supply Data Signal Positive Input Data Signal Negative Input Positive Power Supply Connect to GND or VCC
Rev. 0 | Page 6 of 16
02461-016
ADN2525 TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25C, VCC = 3.3 V, unless otherwise noted.
28.0 27.5
DETERMINISTIC JITTER (ps p-p)
02461-004
9 8 7 6 5 4 3 2 1
02461-007 02461-009 02461-008
27.0 26.5
RISE TIME (ps)
26.0 25.5 25.0 24.5 24.0 23.5 23.0 0 20 40 60 80 DIFFERENTIAL MODULATION CURRENT (mA) 100
0 0 20 40 60 80 DIFFERENTIAL MODULATION CURRENT (mA) 100
Figure 5. Rise Time vs. IMOD
Figure 8. Deterministic Jitter vs. IMOD
27.5 27.0 26.5 26.0
FALL TIME (ps) TOTAL SUPPLY CURRENT (mA)
350 300 250 200 150 100 50 0 0 20 40 60 80 DIFFERENTIAL MODULATION CURRENT (mA) 100 IBIAS = 100mA IBIAS = 50mA IBIAS = 10mA
25.5 25.0 24.5 24.0 23.5
02461-005
23.0 0 20 40 60 80 DIFFERENTIAL MODULATION CURRENT (mA) 100
Figure 6. Fall Time vs. IMOD
0.7
Figure 9. Total Supply Current vs. IMOD
0
0.6
RANDOM JITTER (ps RMS)
-5 -10
DIFFERENTIAL |S11| (dB)
0.5 0.4 0.3 0.2 0.1
-15 -20 -25 -30 -35
0
20 40 60 80 DIFFERENTIAL MODULATION CURRENT (mA)
100
02461-006
0
-40 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FREQUENCY (GHz)
Figure 7. Random Jitter vs. IMOD
Figure 10. Differential |S11|
Rev. 0 | Page 7 of 16
ADN2525
0 -5 -10 -15 -20 -25 -30 -35
02461-010
(ACQ LIMIT TEST) WAVEFORMS: 1000
DIFFERENTIAL |S22| (dB)
-40 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FREQUENCY (GHz)
Figure 11. Differential |S22|
Figure 14. Electrical Eye Diagram (10.7 Gbps, PRBS31, IMOD = 80 mA)
16 14 12
% OCCURRENCE
10 8 6 4 2
02461-011
23
24
25
26 27 RISE TIME (ps)
28
29
30
Figure 12. Worst-Case Rise Time Distribution (VCC = 3.07 V, IBIAS = 100 mA, IMOD = 80 mA, TA = 85C)
Figure 15. Filtered SONET OC192 Optical Eye Diagram (for reference) (PRBS31 Pattern, Pav = -2 dBm, ER = 7 dB, 17% Mask Margin, NEC NX8341UJ TOSA)
16 14 12
% OCCURRENCE
10 8 6 4 2
02461-012
23
24
25
26 27 FALL TIME (ps)
28
29
30
Figure 13. Worst-Case Fall Time Distribution (VCC = 3.07 V, IBIAS = 100 mA, IMOD = 80 mA, TA = 85C)
Figure 16. Filtered 10G Ethernet Optical Eye (PRBS31 Pattern, Pav = -2 dBm, ER = 5 dB, 41% Mask Margin, NEC NX8341UJ TOSA)
Rev. 0 | Page 8 of 16
02461-015
0
02461-014
0
02461-013
ADN2525 THEORY OF OPERATION
As shown in Figure 1, the ADN2525 consists of an input stage and two voltage controlled current sources for bias and modulation. The bias current is available at the IBIAS pin. It is controlled by the voltage at the BSET pin, and can be monitored at the IBMON pin. The differential modulation current is available at the IMODP and IMODN pins. It is controlled by the voltage at the MSET pin. The output stage implements the active backmatch circuitry for proper transmission line matching and power consumption reduction. The ADN2525 can drive a load having differential resistance ranging from 5 to 50 . The excellent back-termination in the ADN2525 absorbs signal reflections from the TOSA end of the output transmission lines, enabling excellent optical eye quality to be achieved even when the TOSA end of the output transmission lines is significantly mis-terminated. The ADN2525 input stage must be ac-coupled to the signal source to eliminate the need for matching between the commonmode voltages of the data signal source and the input stage of the driver (see Figure 18). The ac-coupling capacitors should have an impedance less than 50 over the required frequency range. Generally this is achieved using 10 nF to 100 nF capacitors.
50 50 C
ADN2525
DATAP DATAN
C
DATA SIGNAL SOURCE
INPUT STAGE
The input stage of the ADN2525 converts the data signal applied to the DATAP and DATAN pins to a level that ensures proper operation of the high speed switch. The equivalent circuit of the input stage is shown in Figure 17.
VCC
Figure 18. AC-Coupling the Data Source to the ADN2525 Data Inputs
BIAS CURRENT
The bias current is generated internally using a voltage-to-current converter consisting of an internal operational amplifier and a transistor as shown in Figure 19.
ADN2525
VCC R R IBMON BSET 800 IBMON IBIAS IBIAS
DATAP 50 VCC
VCC 50
02461-017
DATAN
Figure 17. Equivalent Circuit of the Input Stage
GND
The DATAP and DATAN pins are terminated internally with a 100 differential termination resistor. This minimizes signal reflections at the input, which could otherwise lead to degradation in the output eye diagram. It is not recommended to drive the ADN2525 with single-ended data signal sources.
Figure 19. Voltage-to-Current Converter Used to Generate IBIAS
The voltage-to-current conversion factor is set at 100 mA/V by the internal resistors, and the bias current is monitored using a current mirror with a gain equal to 1/100. By connecting a 1 k resistor between IBMON and GND, the bias current can be monitored as a voltage across the resistor. A low temperature coefficient precision resistor must be used for the IBMON resistor (RIBMON). Any error in the value of RIBMON due to tolerances, or drift in its value over temperature, contributes to the overall error budget for the IBIAS monitor voltage. If the IBMON voltage is being connected to an ADC for A/D conversion, RIBMON should be placed close to the ADC to minimize errors due to voltage drops on the ground plane.
Rev. 0 | Page 9 of 16
02461-019
200
200
2
02461-018
ADN2525
The equivalent circuits of the BSET, IBIAS, and IBMON pins are shown in Figure 20, Figure 21, and Figure 22.
VCC VCC BSET 800 200
02461-020
two bias current levels (10 mA and 100 mA), but it can be calculated for any bias current by using the following equation: VCOMPLIANCE_MAX(V) = VCC(V) - 0.75 - 4.4 x IBIAS(A) See the Applications Information section for example headroom calculations. The function of the inductor L is to isolate the capacitance of the IBIAS output from the high frequency signal path. For recommended components, see Table 5.
Figure 20. Equivalent Circuit of the BSET Pin
AUTOMATIC LASER SHUTDOWN (ALS)
IBIAS VCC VCC 2k
The ALS pin is a digital input that enables/disables both the bias and modulation currents, depending on the logic state applied, as shown in Table 4. Table 4.
ALS Logic State High Low Floating IBIAS and IMOD Disabled Enabled Enabled
02461-021
100
2
Figure 21. Equivalent Circuit of the IBIAS Pin
VCC
VCC 500
The ALS pin is compatible with 3.3 V CMOS and TTL logic levels. Its equivalent circuit is shown in Figure 24.
VCC
VCC
100
02461-022
100
ALS
02461-024
VCC IBMON
50k
2k
Figure 24. Equivalent Circuit of the ALS Pin
Figure 22. Equivalent Circuit of the IBMON Pin
MODULATION CURRENT
The modulation current can be controlled by applying a dc voltage to the MSET pin. This voltage is converted into a dc current by using a voltage-to-current converter using an operational amplifier and a bipolar transistor as shown in Figure 25.
VCC IMODP
The recommended configuration for BSET, IBIAS, and IBMON is shown in Figure 23.
TO LASER CATHODE L IBIAS IBIAS
ADN2525
BSET GND IBMON RIBMON 1k
02461-023
VBSET
IMOD
50 IMODN
FROM INPUT STAGE MSET 800
Figure 23. Recommended Configuration for BSET, IBIAS, and IBMON Pins
The circuit used to drive the BSET voltage must be able to drive the 1 k input resistance of the BSET pin. For proper operation of the bias current source, the voltage at the IBIAS pin must be between the compliance voltage specifications for this pin over supply, temperature, and bias current range. See the Specifications table. The maximum compliance voltage is specified for only
ADN2525
GND
Figure 25. Generation of Modulation Current on the ADN2525
Rev. 0 | Page 10 of 16
02461-025
200
ADN2525
This dc current is switched by the data signal applied to the input stage (DATAP and DATAN pins) and gained up by the output stage to generate the differential modulation current at the IMODP and IMODN pins. The output stage also generates the active back-termination, which provides proper transmission line termination. Active back-termination uses feedback around an active circuit to synthesize a broadband termination resistance. This provides excellent transmission line termination, while dissipating less power than a traditional resistor passive back-termination. The equivalent circuits for MSET, IMODP, and IMODN are shown in Figure 26 and Figure 27.
VCC VCC
The ratio between the voltage applied to the MSET pin and the differential modulation current available at the IMODP and IMODN pins is a function of the load resistance value as shown in Figure 29.
210 200 190 180 170 160 150
mA/V
MAXIMUM TYPICAL MINIMUM
140 130 120 110 100 90 80 70
800
02461-026
0
5
10
15 20 25 30 35 40 45 DIFFERENTIAL LOAD RESISTANCE
50
55
200
Figure 29. MSET Voltage to Modulation Current Ratio vs. Differential Load Resistance
Figure 26. Equivalent Circuit of the MSET Pin
VCC 25
IMODN
IMODP
VCC 25
Using the resistance of the TOSA, the user can calculate the voltage range that should be applied to the MSET pin to generate the required modulation current range (see the example in the Applications Information section). The circuit used to drive the MSET voltage must be able to drive the 1 k resistance of the MSET pin. To be able to drive 80 mA modulation currents through the differential load, the output stage of the ADN2525 (IMODP, IMODN pins) must be ac-coupled to the load. The voltages at these pins have a dc component equal to VCC, and an ac component with singleended peak-to-peak amplitude of IMOD x 25 . This is the case even if the load impedance is less than 50 differential, since the transmission line characteristic impedance sets the peak-to-peak amplitude. For proper operation of the output stage, the voltages at the IMODP and IMODN pins must be between the compliance voltage specifications for this pin over supply, temperature, and modulation current range as shown in Figure 30. See the Applications Information section for example headroom calculations.
VIMODP, IMODN
3.3
3.3
02461-027
Figure 27. Equivalent Circuit of the IMODP and IMODN Pins
The recommended configuration of the MSET, IMODP, and IMODN pins is shown in Figure 28. See Table 5 for recommended components.
IBIAS
VCC
ADN2525
Z0 = 25 IMODP
L C
L Z0 = 25
TOSA Z0 = 25 MSET VMSET IMODN GND
02461-028
C
Z0 = 25
VCC + 1.1V
NORMAL OPERATION REGION
L
L
VCC
VCC VCC
VCC - 1.1V
Figure 28. Recommended Configuration for the MSET, IMODP, and IMODN Pins
02461-030
Figure 30. Allowable Range for the Voltage at IMODP and IMODN
Rev. 0 | Page 11 of 16
02461-029
MSET
60
ADN2525
LOAD MIS-TERMINATION
Due to its excellent S22 performance, the ADN2525 can drive differential loads that range from 5 to 50 . In practice, many TOSAs have differential resistance less than 50 . In this case, with 50 differential transmission lines connecting the ADN2525 to the load, the load end of the transmission lines are mis-terminated. This mis-termination leads to signal reflections back to the driver. The excellent back-termination in the ADN2525 absorbs these reflections, preventing their reflection back to the load. This enables excellent optical eye quality to be achieved, even when the load end of the transmission lines is significantly mis-terminated. The connection between the load and the ADN2525 must be made with 50 differential (25 single-ended) transmission lines so that the driver end of the transmission lines is properly terminated.
THERMAL COMPOUND MODULE CASE
TTOP
DIE PACKAGE
TJ
T PAD
THERMO-COUPLE
PCB
02461-031
COPPER PLANE VIAS
Figure 31. Typical Optical Module Structure
The following procedure can be used to estimate the IC junction temperature: TTOP = Temperature at top of package in C. TPAD = Temperature at package exposed paddle in C. TJ = IC junction temperature in C. P = Power dissipation in W. J-TOP = Thermal resistance from IC junction to package top. J-PAD = Thermal resistance from IC junction to package exposed pad.
TTOP
POWER CONSUMPTION
The power dissipated by the ADN2525 is given by
V P = VCC x MSET + I SUPPLY + V IBIAS x IBIAS 13.5
where: VCC is the power supply voltage. IBIAS is the bias current generated by the ADN2525. VMSET is the voltage applied to the MSET pin. ISUPPLY is the sum of the current that flows into the VCC, IMODP, and IMODN pins of the ADN2525 when IBIAS = IMOD = 0 expressed in amps (see Table 1). VIBIAS is the average voltage on the IBIAS pin. Considering VBSET/IBIAS = 10 as the conversion factor from VBSET to IBIAS, the dissipated power becomes
V V P = VCC x MSET + I SUPPLY + BSET x VIBIAS 13.5 10
J-TOP
TTOP
P
J-PAD
TPAD TPAD
02461-032
Figure 32. Electrical Model for Thermal Calculations
To ensure long-term reliable operation, the junction temperature of the ADN2525 must not exceed 125C, as specified in Table 2. For improved heat dissipation, the module's case can be used as heat sink as shown in Figure 31. A compact optical module is a complex thermal environment, and calculations of device junction temperature using the package JA (junction-toambient thermal resistance) do not yield accurate results.
TTOP and TPAD can be determined by measuring the temperature at points inside the module as shown in Figure 31. The thermocouples should be positioned to obtain an accurate measurement of the package top and paddle temperatures. Using the model shown in Figure 32, the junction temperature can be calculated using the following formula:
TJ = P x J -PAD x J -TOP + TTOP x J -PAD + TPAD x J -TOP J -PAD + J -TOP
(
)
where J-TOP and J-PAD are given in Table 2 and P is the power dissipated by the ADN2525.
Rev. 0 | Page 12 of 16
ADN2525 APPLICATIONS INFORMATION
TYPICAL APPLICATION CIRCUIT
Figure 33 shows the typical application circuit for the ADN2525. The dc voltages applied to the BSET and MSET pins control the bias and modulation currents. The bias current can be monitored as a voltage drop across the 1 k resistor connected between the IBMON pin and GND. The ALS pin allows the user to turn on/off the bias and modulation currents, depending on the logic level applied to the pin. The data signal source must be connected to the DATAP and DATAN pins of the ADN2525 using 50 transmission lines. The modulation current outputs, IMODP and IMODN, must be connected to the load (TOSA) using 50 differential (25 single-ended) transmission lines. Table 5 shows recommended components for the ac-coupling interface between the ADN2525 and TOSA. For up-to-date component recommendations, contact your sales representative. Table 5.
Component R1, R2 R3, R4 C3, C4 L2, L3, L6, L7 L1, L4, L5, L8 Value 36 200 100 nF 82 nH 10 H Description 0603 size resistor 0603 size resistor 0603 size capacitor, Phycomp 223878615649 0402 size inductor, Murata LQW15AN82NJ0 0603 size inductor, Murata LQM21FN100M70L
LAYOUT GUIDELINES
Due to the high frequencies at which the ADN2525 operates, care should be taken when designing the PCB layout to obtain optimum performance. Controlled impedance transmission lines must be used for the high speed signal paths. The length of the transmission lines must be kept to a minimum to reduce losses and pattern-dependent jitter. The PCB layout must be symmetrical, both on the DATAP, DATAN inputs, and on the IMODP, IMODN outputs, to ensure a balance between the differential signals. All VCC and GND pins must be connected to solid copper planes by using low inductance connections. When the connections are made through vias, multiple vias can be connected in parallel to reduce the parasitic inductance. Each GND pin must be locally decoupled with high quality capacitors. If proper decoupling cannot be achieved using a single capacitor, the user can use multiple capacitors in parallel for each GND pin. A 20 F tantalum capacitor must be used as general decoupling capacitor for the entire module. For guidelines on the surface-mount assembly of the ADN2525, consult the Amkor Technology(R) application note "Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame(R) (MLF) Packages."
GND
VCC R5 1k GND C5 10nF VCC L1 R1 L8 R4
BSET
TP1
VCC Z0 = 50 DATAP C1
BSET IBMON IBIAS GND VCC VCC
VCC Z0 = 25
L2
L7 Z0 = 25 C4 TOSA Z0 = 25 C3 L6
DATAP
IMODP
ADN2525
Z0 = 50 DATAN C2 VCC VCC MSET NC1 VCC GND DATAN IMODN
GND Z0 = 25 GND L3 VCC
ALS
VCC MSET +3.3V VCC C7 20F GND ALS C6 10nF GND VCC VCC
02461-033
L4
R2
L5
R3
Figure 33. Typical ADN2525 Application Circuit
Rev. 0 | Page 13 of 16
ADN2525
DESIGN EXAMPLE
This design example covers * * Headroom calculations for IBIAS, IMODP, and IMODN pins. Calculation of the typical voltage required at the BSET and MSET pins in order to produce the desired bias and modulation currents. Assuming VLB = 0 V and IMOD = 60 mA, the minimum voltage at the modulation output pins is equal to VCC - (IMOD x 25)/2 = VCC - 0.75 VCC - 0.75 > VCC - 1.1 V, which satisfies the requirement. The maximum voltage at the modulation output pins is equal to VCC + (IMOD x 25)/2 = VCC + 0.75 VCC + 0.75 < VCC + 1.1 V, which satisfies the requirement. Headroom calculations must be repeated for the minimum and maximum values of the required IBIAS and IMOD ranges to ensure proper device operation over all operating conditions.
This design example assumes that the resistance of the TOSA is 25 , the forward voltage of the laser at low current is VF = 1 V, IBIAS = 40 mA, IMOD = 60 mA, and VCC = 3.3 V.
Headroom Calculations
To ensure proper device operation, the voltages on the IBIAS, IMODP, and IMODN pins must meet the compliance voltage specifications in Table 1. Considering the typical application circuit shown in Figure 33, the voltage at the IBIAS pin can be written as VIBIAS = VCC - VF - (IBIAS x RTOSA) - VLA where: VCC is the supply voltage. VF is the forward voltage across the laser at low current. RTOSA is the resistance of the TOSA. VLA is the dc voltage drop across L5, L6, L7, and L8. VLB is the dc voltage drop across L1, L2, L3, and L4. For proper operation, the minimum voltage at the IBIAS pin should be greater than 0.6 V, as specified by the minimum IBIAS compliance specification in Table 1. Assuming that the voltage drop across the 25 transmission lines is negligible and that VLA =0 V, VF = 1 V, IBIAS = 40 mA, VIBIAS = 3.3 - 1 - (0.04 x 25) = 1.3 V VIBIAS = 1.3 V > 0.6 V, which satisfies the requirement. The maximum voltage at the IBIAS pin must be less than the maximum IBIAS compliance specification as described by the following equation: VCOMPLIANCE_MAX = VCC - 0.75 - 4.4 x IBIAS(A) For this example: VCOMPLIANCE_MAX = VCC - 0.75 - 4.4 x 0.04 = 2.53 V VIBIAS = 1.3 V < 2.53 V, which satisfies the requirement. To calculate the headroom at the modulation current pins (IMODP, IMODN), the voltage has a dc component equal to VCC due to the ac-coupled configuration and a swing equal to IMOD x 25 . For proper operation of the ADN2525, the voltage at each modulation output pin should be within the normal operation region shown in Figure 30.
BSET and MSET Pin Voltage Calculation
To set the desired bias and modulation currents, the BSET and MSET pins of the ADN2525 must be driven with the appropriate dc voltage. The voltage range required at the BSET pin to generate the required IBIAS range can be calculated using the BSET voltage to IBIAS gain specified in Table 1. Assuming that IBIAS = 40 mA and the typical IBIAS/VBSET ratio of 100 mA/V, the BSET voltage is given by
VBSET = IBIAS(mA) 40 = = 0.4 V 100 mA/V 100
The BSET voltage range can be calculated using the required IBIAS range and the minimum and maximum BSET voltage to IBIAS gain values specified in Table 1. The voltage required at the MSET pin to produce the desired modulation current can be calculated using
VMSET = IMOD K
where K is the MSET voltage to IMOD ratio. The value of K depends on the actual resistance of the TOSA. It can be read using the plot shown in Figure 29. For a TOSA resistance of 25 , the typical value of K = 120 mA/V. Assuming that IMOD = 60 mA and using the preceding equation, the MSET voltage is given by
VMSET = IMOD(mA) 60 = = 0.5 V 120 mA/V 120
The MSET voltage range can be calculated using the required IMOD range and the minimum and maximum K values. These can be obtained from the minimum and maximum curves in Figure 29.
Rev. 0 | Page 14 of 16
ADN2525 OUTLINE DIMENSIONS
0.50 0.40 0.30 PIN 1 INDICATOR
16 1
3.00 BSC SQ 0.45 PIN 1 INDICATOR TOP VIEW 2.75 BSC SQ 0.50 BSC 12 MAX 1.00 0.85 0.80 SEATING PLANE 0.30 0.23 0.18 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.20 REF
0.60 MAX
13 12
1.65 1.50 SQ* 1.35
EXPOSED PAD
9 (BOTTOM VIEW) 4 8 5
0.25 MIN
1.50 REF
*COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION
Figure 34. 16-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm x 3 mm Body (CP-16-3) Dimensions shown in millimeters
ORDERING GUIDE
Model ADN2525ACPZ-WP1 ADN2525ACPZ-R21 ADN2525ACPZ-REEL71
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C
Package Description 16-Lead Lead Frame Chip Scale Package, 50-Piece Waffle Pack 16-Lead Lead Frame Chip Scale Package, 500-Piece Reel 16-Lead Lead Frame Chip Scale Package, 7" 1500-Piece Reel
Package Option CP-16-3 CP-16-3 CP-16-3
Branding F06 F06 F06
Z = Pb-free part.
Rev. 0 | Page 15 of 16
ADN2525 NOTES
(c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05077-0-3/05 (0)
Rev. 0 | Page 16 of 16

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